1. Field of the Invention
The present invention relates to an adder with reverse carry system.
2. Description of the Prior Art
FIG. 1 shows the conventional adder. Two inputs a and b of the add objects are inputted into an exclusive OR gate 1a and an output thereof is given as one input into an exclusive OR gate 1b and also given into an inverter 2, a carry input c being given as the other input into the exclusive OR gate 1b.
The output of the exclusive OR gate lb is the sum output d.
The inputs b and c are also given to drains of NMOS transistors 5a and 5b, the sources of which are adapted to be connected in batch to obtain an output e, the output of the exclusive OR gate 1a is given to the gate of transistor 5b, the output of the inverter 2 being given to the gate of transistor 5a.
The transistors 5a and 5b serve as a selector for equalizing potential at the terminal of carry output e to that at the terminal of the input b or to that at the terminal of the input c.
Table 1 shows the table of truth value of the adder.
TABLE 1 ______________________________________ Input Carry Output Sum Output a b c e d ______________________________________ 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 ______________________________________
Referring to FIG. 2, an adding circuit is shown which comprises eight connected adders P shown in FIG. 1, in which reference letters i.sub.0, i.sub.1, i.sub.2 . . . i.sub.7 designate the first inputs for the eight bits and serving as the inputs a for the adders P respectively.
Each carry output e at the lower-order bit side is used as the input c at the higher-order bit side, the input c of the adder P at the lowest-order bit is put at earth potential, and the carry output e at the adder P at the highest-order bit is the carry output K8 of the adding circuit. The sum outputs d of the adders P are outputted as the sum K0, K1, K2 . . . K7 of the adding circuit.
The adder P shown in FIG. 1 may carry out bit reverse address computation used in FFT (Fast Fourier Transform). In this case, as shown in FIG. 3, the respective functions of the carry input and carry output are reverse to those shown in FIG. 2 in the circuit structure. The adding circuit shown in FIG. 3 is called the bit reverse adding circuit. In detail, the carry output e at the higher-order bit side is connected to the carry input c at the lower-order bit side, the input c at the highest-order bit is put earth potential, the carry output e at the lowest-order bit is used as the carry output K8.
The inputs i.sub.0, i.sub.1, i.sub.2 . . . i.sub.7 and j.sub.0, j.sub.1, j.sub.2 . . . j.sub.7 to be added are called the base addresses. In a case where FFT for 8 points at the base addresses i.sub.7 . . . i.sub.2, i.sub.1, i.sub.0 =(10000000).sub.2, the base addresses j.sub.7 . . . j.sub.2, j .sub.1, j.sub.0 =(00000100).sub.2 are sequentially added.
The sum output in the above case is as follows:
______________________________________ Number of Addition Times K7 K2, K1, K0 ______________________________________ 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 2 1 0 0 0 0 1 0 3 1 0 0 0 1 1 0 4 1 0 0 0 0 0 1 5 1 0 0 0 1 1 1 6 1 0 0 0 0 1 1 7 1 0 0 0 1 1 1 ______________________________________
Thus, the bit reverse address at FFT is obtained.
Since the conventional adder is constructed as shown in FIG. 1, when the bit reverse address computation is carried out, the circuit shown in FIG. 2 cannot cope with the bit reverse computation, whereby an exclusive circuit as shown in FIG. 3 is required to be prepared.